1. Field of the Invention
This invention relates to SRAM and to processes for making SRAM.
2. Description of Related Art
Static random access memory (SRAM) is well known and commonly employs either four-transistor or six-transistor cells. FIG. 1 shows a six-transistor SRAM cell 100 having two pass transistors 131 and 132 which connect respective internal nodes 141 and 142 to respective bit lines 151 and 152 when a voltage on a word-line 160 is asserted. The remaining transistors in SRAM cell 100 are P-channel pull-up transistors 111 and 112 and N-channel pull-down transistors 121 and 122 which control the voltages on internal nodes 141 and 142. P channel pull-up transistors 111 and 112 are between respective nodes 141 and 142 and a supply voltage Vcc and have gates cross-coupled to opposite nodes 142 and 141 respectively. N-channel pull-down transistors 121 and 122 are between respective nodes 141 and 142 and ground (reference voltage Vss) and have gates cross-coupled to opposite nodes 142 and 141 respectively.
In steady state operation, the voltages on nodes 141 and 142 are complementary and indicate a value of a bit stored in SRAM cell 100. Voltage on node 141 being high turns off transistor 112 and turns on transistor 122 which pulls node 142 low. Voltage on node 142 being low turns off transistor 121 and turns on transistor 111 which pulls node 141 high. When voltage on node 141 is low, transistor 122 is off, and transistor 112 is on to pull node 142 high. Node 142 being high turns off transistor 111 and turns on transistor 121 to pull node 141 low.
A goal for SRAM cells in an integrated circuit is a compact layout of transistors and interconnects, but the layout must allow for anticipated alignment errors during manufacture and provide isolation between active regions. Additionally, manufacturing should achieve a high yield of operable integrated circuits using a relatively simple process that minimizes manufacturing steps to reduce cost. The layout should also provide a robust cell that is fast and not subject to errors that cause a stored value to erroneously change. A layout and manufacturing process for a six-transistor SRAM cell that achieves these goals is sought.